publications

2021

1. Stealth Attack on Protected DNNs: Compromising Robustness without Losing Accuracy via Smart Bit Flipping

   B. Ghavami, S.H. Mousavi, Z. Fang, and 1 more author

   Design Automation Conference 2021 (DAC), Dec 2021

   WIP
2. LEAP: A Deep Learning based Aging-Aware Architecture Exploration Framework for FPGAs

   B. Ghavami, S.M. Ebrahimipour, Z. Fang, and 1 more author

   Proc. ACM/SIGDA Int. Symp. Field-Programmable Gate Arrays (FPGA), Feb 2021

   Poster
3. Soft Error Reliability of VLSI Circuits: Analysis and Mitigation Techniques

   B. Ghavami, and M. Raji

   Feb 2021

2020

1. Aadam: A Fast, Accurate, and Versatile Aging-Aware Cell Library Delay Model using Feed-Forward Neural Network

   S.M. Ebrahimipour, B. Ghavami, H. Mousavi, and 3 more authors

   IEEE/ACM International Conference On Computer Aided Design (ICCAD), Nov 2020
2. Timing Reliability Improvement of Master-Slave Flip-Flops in the Presence of Aging Effects

   A. Jafari, M. Raji, and B. Ghavami

   IEEE Transactions on Circuits and Systems I: Regular Papers (IEEE TCAS), Nov 2020
3. A Statistical Gate Sizing Method for Timing Yield and Lifetime Reliability Optimization of Integrated Circuits

   S.M. Ibrahimi, B. Ghavami, and M. Raji

   IEEE Transactions on Emerging Topics (IEEE TETC) in Computing, Nov 2020

2019

1. Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuits

   S.M. Ebrahimipour, B. Ghavami, and M. Raji

   IET Circuits, Devices & Systems, Nov 2019
2. Improving Combinational Circuit Reliability Against Multiple Event Transients via a Partition and Restructuring Approach

   M.R. Rohanipoor, B. Ghavami, and M. Raji

   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Nov 2019
3. Impacts of Process Variations and Aging on Lifetime Reliability of Flip-Flops: A Comparative Analysis

   A. Jafari, M. Raji, and B. Ghavami

   IEEE Transactions on Device and Materials Reliability (IEEE TDMR), Nov 2019

2018

1. An incremental algorithm for soft error rate estimation of combinational circuits

   B. Ghavami, M. Raji, K. Saremi, and 1 more author

   IEEE Transactions on Device and Materials Reliability (IEEE TDMR), Nov 2018

2017

1. A scalable solution to soft error tolerant circuit design using partitioning-based gate sizing

   M.A. Sabet, B. Ghavami, and M. Raji

   IEEE Transactions on Reliability (IEEE TR), Nov 2017

2016

1. Soft error rate reduction of combinational circuits using gate sizing in the presence of process variations

   M. Raji, and B. Ghavami

   IEEE Transactions on Very Large Scale Integration Systems (IEEE TVLSI), Nov 2016
2. Failure characterization of carbon nanotube FETs under process variations: technology scaling issues

   B. Ghavami, and M. Raji

   IEEE Transactions on Device and Materials Reliability (IEEE TMR), Nov 2016

2015

1. Soft error rate estimation of combinational circuits based on vulnerability analysis

   M. Raji, H. Pedram, and B. Ghavami

   IET Computers & Digital Techniques, Nov 2015

2013

1. Design and analysis of a robust carbon nanotube-based asynchronous primitive circuit

   B. Ghavami, M. Raji, H. Pedram, and 1 more author

   ACM Journal on Emerging Technologies in Computing Systems (JETC), Nov 2013

2012

1. Statistical functional yield estimation and enhancement of CNFET-based VLSI circuits

   B. Ghavami, M. Raji, H. Pedram, and 1 more author

   IEEE transactions on very large scale integration (VLSI) systems (IEEE TVLSI), Nov 2012

2011

1. A statistical-based material and process guidelines for design of carbon nanotube field-effect transistors in gigascale integrated circuits

   B. Ghavami, M. Raji, and H. Pedram

   Nanotechnology, Nov 2011